Multiplexer Output Glitching

That is the major problem with asynchronous logic and FPGAs: they are not made for each other. Almost all FPGAs are pure synchronous beasts. (Except Achronix and maybe some newer start-up).

You are right about those 12 LE's to implement the 4 to 1 hazard free mux. A 4 input LUT isn't that powerful: it only enables you to decode one of the 16 squares in the corresponding Karnaugh map.

The code you propose to build a 2 to 1 mux is not hazard free:

assign x = (t) ? d : c;

will translate into

  x = !t & c
    |  t & d
    ;

Where the hazard elimination term "| a & b" is missing.