Honored Contributor
Honored ContributorHi Josyb,
Your code makes the assumption that a two input AND and three input NOR doesn't glitch when a single input changes in a state which doesn't change the output. For example with an AND gate with inputs a and b, if a = 0 and b changes from 0 to 1 you would expect the output to stay at 0 and not glitch to 1. If this assumption is false, there isn't anything you can do about it to make you whole circuit glitch free. Now the assumption of a two input gate not glitching is likely to be true as it will always fit into a single LE which I believe to be glitch free. However a three input gate could be potentially be spread across two LEs depending on how the fitter decides to do things. Once spread across multiple LEs a three input gate will potentially have glitches in its output. Now in your design, you have the synthesis keep option so each logic statement will be in its own LE and the overall design will be glitch free. The downside is that is complicated and I guess will use 12 LEs. (I can't check this nor anything else at the moment as my main computer decided to allow a power inductor to fall out of the power supply PCB and is currently rattling around the case - this isn't recommended...) If you make the assumption that a single LE is glitch free by design then ANY combinatorial logic with up to 4 inputs will be glitch free as it will fit into a single LE. This then enables a 4 to 1 mux to be made glitch free from 3 LEs using the code below. wire x,y /* synthesis keep */;
assign x = (t) ? d : c;
assign y = (t) ? b : a;
assign q = (s) ? x : y;
