Multiplexer Output Glitching

I couldn't keep from searching a bit deeper and went back to some 'old' textbooks.

I.e. what we call a glitch here is in effect called a 'logic hazard'. Making hazard free circuits for a single input changing is relatively easy by adding 'redundant' (at first sight) coverage terms. For a logic hazard free 2 to 1 mux it looks like this

 
 y = !s & a
   |  s & b
   |  a & b
   ;

Unfortunately the 3rd term eliminating the logic hazard will optimized away, so the equation becomes abit elaborate

 wire gab , gcd , gabcd,  hab, hcd , habcd , iab , icd , iabcd , rab , rcd/* synthesis keep*/ ;
 assign  gab = !s & a0 ;
 assign  hab =  s & b0 ;
 assign  iab = a0 & b0 ;
 assign  rab = gab | hab | iab ;
	
 assign  gcd = !s & c0 ;
 assign  hcd =  s & d0 ;
 assign  icd = c0 & d0 ;
 assign  rcd = gcd | hcd | icd ;
	
 assign  gabcd = !t & rab ;
 assign  habcd =  t & rcd ;
 assign  iabcd = rab & rcd ;
 assign  q0 = gabcd | habcd | iabcd ;

This will generate a hazard-free 4 to 1 multiplexer for a single input change.

It should be possible to harness a 2 to 1 mux with hazard-coverage into a single LUT, but we may need some help form Altera here to 'tame' the optimizer.