Multiplexer Output Glitching

I think you are wrong but please don't take that the wrong way, I'm not 100% sure that I'm right and would like to discuss this until we are both happy that we understand what is going on. Please rip anything I say to shreds so we can get to the bottom of it and both learn.

x = (!t & c) | (t & d) will be implemented in the LUT as follows:

c d t | x
=========
0 0 0 | 0
0 0 1 | 0
0 1 0 | 0
0 1 1 | 1
1 0 0 | 1
1 0 1 | 0
1 1 0 | 1
1 1 1 | 1

Now from the above, it is easy to see that if c and d are the same value then the output won't change when t changes value. Now if the LUT is designed to be glitch free (which I am very sure it would have to be) then the output won't glitch as it is just moving from one row in the LUT to the next. No additional logic is required.

Now if instead of being made from a LUT, the logic was being made from two AND gates and an OR gate then I would agree with you, the design would potentially glitch and the extra logic is required to stop this. However, it isn't, it is made from a LUT so the extra logic isn't required as long as the LUT was designed to be glitch free when swapping between rows with a single input change.

Now I'm pretty confident that the LUT is designed to be glitch free as if it wasn't simple logic gates such as ANDs and ORs would also glitch and there would be complaints everywhere. I do need to get this confirmed though as my design now relies on this fact. I can't find anything in the Altera docs though. I will keep on trying.

I also agree that asynchronous logic in FPGAs is a minefield and very difficult to get right. If anybody else reading this thread wants to pitch in then please do.