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Now I'm pretty confident that the LUT is designed to be glitch free as if it wasn't simple logic gates such as ANDs and ORs would also glitch and there would be complaints everywhere. I do need to get this confirmed though as my design now relies on this fact. I can't find anything in the Altera docs though. I will keep on trying.
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We talked about this a couple of times here. Search the forum for "LUT glitches".
The bad news is that this is mostly an undocumented feature. For some reason it seems to be undocumented on most other FPGA vendors as well. The concensus seems to be that LUT is, by design glitch free for a single input change, but it might be not if two or more inputs change at the same time. There were some doubts if this applies to ALUTs as well.
But then, the relevant question is how far apart the change in two LUT inputs should be for avoiding glitches. And of course, not being a formally documented parameter, nobody would tell you.
Basically, this agrees with josyb statement, that FPGAs are synchronous beasts. They were not designed for async logic, quite the contrary. And it is not just the silicon, but the tools and documentation as well. This doesn't mean, of course, it is totally impossible to implement async logic.
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