Multiplexer Output Glitching

Now if you only have to consider one input changing at at time, your above design with the 'keep' attributes seems to work best without glitching as 't' works on the first tier while 's' decides on the second tier in the purposely designed 2-tier logic. We now have 3 times the same circuit. But in theory even the simple circuit which muxes two inputs onto one output could glitch when the output selection tuns off faster than the other selection turns on. So if we could force a 'delayed' turnoff we would be glitchfree by design. But here we depend on the physical process in the LUT. In the days of TTL logic we could select devices with a TpHL > TpLH. We could infer that the same may be true inside an FPGA, but this might just be wishful thinking. Maybe you could ask Altera about the LUT TpLH and TpHL of the device you are using?