MAX10M04 / Quartus Prime Lite Edition

Hi,

I tried compiling your project on my machine and it seems to work fine. Can you let me know what OS are you using and can you attach a picture of the error message you receive?

Thanks,

Nurina

P/S: Feel free to give Kudos to comments you find to be helpful.

Hi Gigi,

So just to clarify, the anomaly mode is that when you add the 4th counter it doesn't function correctly while causing the other counters to function wrongly? Is there anything more to it?

Regards,

Nurina

Hi Gigi,

Have you simulated your design and confirmed the functionality? You should verify that your logic on RTL viewer are connecting as intended.

Regards,

Nurina

Hi Gigi,

You can refer to page 3 of this document on how to use it: https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/qts/qts_qii51013.pdf

The Intel FPGA YouTube channel has some videos on it as well, you can start here: https://www.youtube.com/watch?v=nWIGG0eWpJU

Part 2 of the video lecture is available here: https://www.youtube.com/watch?v=gFclHedSomA

In most cases warning messages can be ignored. Can you attach a photo of the warning messages here so I can verify that it can be ignored?

Thanks,

Nurina

Hi Gigi,

Yes, I did. You can ignore most of them, but I suggest you do something about the multiple warnings about overlapping block or symbols. Follow the solution available here: https://www.intel.com/content/www/us/en/programmable/quartushelp/13.0/mergedProjects/msgs/msgs/egdfx_symbols_overlap_error.htm

Also, I've checked your pin planner and it seems that you are using a clock pin for the EXT_ENC4_ALARM node, I think that's the cause of the problem. Use a differential pin for this node like you did with the other ALARM nodes.

Regards,

Nurina

Hi Gigi,

I don't see signals "ENC4_A" and "ENC4_B" connected to the ground in your new design file. Can you explain what those signals, along with the alarm signal do?

Can you use the SignalTap logic analyzer on the 4Encoder to probe and debug the behaviour of internal signals during normal device operation? SignalTap can be used to monitor your real time signal, so you can find the root cause of the problem.

Here's a document that can help you understand SignalTap: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii53009.pdf?wapkw=signal%20tap%20

There are also some training courses about SignalTap available on Intel FPGA's YouTube channel: https://www.youtube.com/watch?v=RtPqQ25hSIk

Regards,

Nurina

Hi Gigi,

You can fix those warnings by constraining the clock signals using Timing Analyzer. Go to Tools->Timing Analyzer.

Here is a reference on it: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

Regards,

Nurina

Hi Gigi,

We did not receive any response to the previous answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

Hi Gigi,

My previous reply suggests you to solve the timing warnings by constraining the clock signals using Timing Analyzer.

So you're trying to figure out why that happens? By solved do you mean that all 4 counters work together as expected?

Regards,

Nurina

Hi Gigi,

It's best to investigate this problem with an RTL simulation. These signals might be affected by other signals or the clock hence behaving unexpectedly.

I know it'll take some time to do that so you can just come back here for consultation on that whenever you're ready.

Best regards,

Nurina