Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)

We are trying to use the Infineon S25FS512S QSPI NOR Flash with Cyclone 10 GX in Active Serial x4 (AS x4) configuration by creating a Custom Flash Definition based on AN229767.

JTAG programming completes successfully, but FPGA configuration fails in AS x4 mode. We have performed extensive debugging and would like to understand whether this is a supported use case or if there are any known limitations.

Observations

Flash Programming

• JTAG programming completes successfully.
• Flash verification completes successfully.

Configuration Behavior

• Active Serial x1 configuration works correctly.
• Active Serial x4 configuration fails.
• The FPGA successfully issues the RDID (0x9F) command.
• The FPGA then attempts to read the Boot Information from address 0x00000000.
  
  
  

Logic Analyzer Observation

During AS x4 configuration, the FPGA issues the EBh (Quad I/O Read) command.

According to the Infineon S25FS512S datasheet, the expected transaction is:

EBh

→ 4-byte Address
→ Mode Byte (8 bits)
→ Dummy Cycles
→ Data

However, the captured waveform shows:

EBh
→ 4-byte Address
→ Dummy Cycles
→ Data

No Mode Byte is observed between the address and dummy cycles.

Based on the S25FS512S command protocol, this could cause the flash to interpret the transaction differently and return misaligned data. We would like Altera to confirm whether this behavior is expected from the Cyclone 10 GX configuration controller.

Additional Information

• We reviewed AN229767, but could not find any mechanism in the Custom Flash Definition to configure or insert the Mode Byte required by the EBh command.
• We also observed that the Custom Flash Definition supports Read Register commands only for fixed register opcodes and does not appear to support RDAR (0x65) with a register address.

Questions

1. Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command?
2. If not, is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer?
3. Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition?
4. Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference?

Environment

• FPGA: Cyclone 10 GX
• Flash: Infineon S25FS512S
• Configuration Mode: Active Serial x1 (working), Active Serial x4 (failing)
• Programming Method: Quartus Programmer using a Custom Flash Definition based on AN229767

We would appreciate any guidance, clarification, or a reference implementation for using the S25FS512S with Cyclone 10 GX in Active Serial x4 mode.