Forum Discussion
Occasional ContributorCyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)
We are trying to use the Infineon S25FS512S QSPI NOR Flash with Cyclone 10 GX in Active Serial x4 (AS x4) configuration by creating a Custom Flash Definition based on AN229767.
JTAG programming completes successfully, but FPGA configuration fails in AS x4 mode. We have performed extensive debugging and would like to understand whether this is a supported use case or if there are any known limitations.
Observations
Flash Programming
- JTAG programming completes successfully.
- Flash verification completes successfully.
Configuration Behavior
- Active Serial x1 configuration works correctly.
- Active Serial x4 configuration fails.
- The FPGA successfully issues the RDID (0x9F) command.
- The FPGA then attempts to read the Boot Information from address 0x00000000.
Logic Analyzer Observation
During AS x4 configuration, the FPGA issues the EBh (Quad I/O Read) command.
According to the Infineon S25FS512S datasheet, the expected transaction is:
EBh
→ 4-byte Address
→ Mode Byte (8 bits)
→ Dummy Cycles
→ Data
However, the captured waveform shows:
EBh
→ 4-byte Address
→ Dummy Cycles
→ Data
No Mode Byte is observed between the address and dummy cycles.
Based on the S25FS512S command protocol, this could cause the flash to interpret the transaction differently and return misaligned data. We would like Altera to confirm whether this behavior is expected from the Cyclone 10 GX configuration controller.
Additional Information
- We reviewed AN229767, but could not find any mechanism in the Custom Flash Definition to configure or insert the Mode Byte required by the EBh command.
- We also observed that the Custom Flash Definition supports Read Register commands only for fixed register opcodes and does not appear to support RDAR (0x65) with a register address.
Questions
- Does the Cyclone 10 GX configuration controller support transmitting the mandatory Mode Byte required by the EBh (Quad I/O Read) command?
- If not, is this a known limitation of the Cyclone 10 GX configuration controller or Quartus Programmer?
- Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition?
- Has Altera validated any Custom Flash Definition for the S25FS512S that can be shared as a reference?
Environment
- FPGA: Cyclone 10 GX
- Flash: Infineon S25FS512S
- Configuration Mode: Active Serial x1 (working), Active Serial x4 (failing)
- Programming Method: Quartus Programmer using a Custom Flash Definition based on AN229767
We would appreciate any guidance, clarification, or a reference implementation for using the S25FS512S with Cyclone 10 GX in Active Serial x4 mode.
10 Replies
Farabi_AlteraRegular Contributor
This is a well-documented and thoroughly debugged report — let me give you a direct answer on each of your questions.
1. Does the Cyclone 10 GX configuration controller support transmitting the Mode Byte required by the EBh (Quad I/O Read) command?
Based on the available documentation, the answer is effectively no. Cyclone 10 GX devices only support 4-byte addressing and 10 dummy clock cycles for single and quad fast read commands. Arria 10 · Config/RSU The configuration controller's AS interface is designed around a fixed command sequence: command opcode → 4-byte address → dummy cycles → data. There is no documented mechanism in the configuration controller to insert an additional Mode Byte between the address phase and the dummy cycles. Your logic analyzer observation — EBh → 4-byte address → dummy cycles → data, with no Mode Byte — is consistent with how the Cyclone 10 GX AS controller operates.
This is the root cause of your AS x4 failure with the S25FS512S. The EBh (Quad I/O Read) command on that device mandates a Mode Byte after the address, and the Cyclone 10 GX controller does not generate it.
2. Is this a known limitation of the Cyclone 10 GX configuration controller?
Yes, this is a fundamental architectural constraint of the AS configuration block, not a software bug. The Active Serial (AS) configuration control block in Arria 10 and Cyclone 10 GX is fixed to 10 dummy clock cycles and 4-byte addressing. Arria 10 · Config/RSU The fixed nature of the command sequencing means the controller cannot be programmed to emit an extra Mode Byte phase. This is why only certain flash devices are validated for AS use with Cyclone 10 GX — the flash must be compatible with the controller's fixed protocol.
3. Is there any supported method to modify the Quad I/O Read command sequence in the Custom Flash Definition?
No. The Custom Flash Definition (Generic Flash Programmer) allows you to define device properties such as device ID, density, I/O voltage, and dummy clock cycles for single and quad I/O modes, but it does not expose a mechanism to insert or configure a Mode Byte in the read command sequence. The "Single I/O mode dummy clock" and "Quad I/O mode dummy clock" settings specify the Fast Read dummy clock cycle for the flash device in single and quad I/O protocols respectively — the programming file generation uses these settings to determine if the configuration requires bit shifting to compensate for the actual dummy clock cycle during Active Serial configuration. Defining a New Flash Memory Device There is no field for a Mode Byte, and the underlying controller hardware does not support it regardless.
Your observation about RDAR (0x65) with a register address is also correct — the Custom Flash Definition's Read Register (RR) action supports fixed-opcode register reads but does not support addressed register commands like RDAR.
4. Recommended path forward
Given this limitation, here are the practical options:
- Stay on AS x1: Since AS x1 works correctly for you, this is the most straightforward path. AS x1 uses a standard Fast Read command that does not require a Mode Byte, so it is fully compatible with the Cyclone 10 GX controller's fixed protocol.
- Switch to a validated flash device: The following Macronix flash devices can be used in Active Serial (x1 and x4) configuration mode with Arria 10 and Cyclone 10 GX: MX25L series (2.7V–3.6V) at 128Mb, 256Mb, and 512Mb densities, and MX25U/MX66U series (1.65V–2.0V) at 256Mb, 512Mb, 1Gb, and 2Gb densities. Arria 10 · Config/RSU These devices use a Quad Fast Read command sequence that is compatible with the controller's fixed protocol.
- Use the Generic Serial Flash Interface IP for runtime access: The legacy ASMI Parallel IP does not support certain Macronix flash devices in AS mode for Arria 10 and Cyclone 10 GX; to use those flash devices, use the Generic Serial Flash Interface Intel FPGA IP core. Arria 10 · Config/RSU Similarly, if you need to use the S25FS512S for data storage or runtime access (not FPGA configuration), the Generic Serial Flash Interface IP gives you full control over the command sequence including any Mode Byte requirements.
- Cypress/Infineon S25FSxxxS with AS x1: AS configuration failure with Cypress S25FSxxxS can occur when flash configuration registers are not set correctly. For AS x1, the flash configuration registers (CR2NV/CR2V) should be set to 0x8A (ASx1 scheme, 4-byte addressing, dummy clock cycles 10). Arria 10 · Config/RSU If you want to pursue AS x1 with the S25FS512S, ensure the register is set correctly and that the .pof/.rpd is generated with the "Disable EPCS/EPCQ ID check" option enabled.
5. Validated Custom Flash Definition for S25FS512S in AS x4: I do not have a validated reference Custom Flash Definition for the S25FS512S in AS x4 mode in the available documentation, and given the Mode Byte constraint described above, such a definition would not be able to work around the hardware limitation. I would not recommend pursuing AS x4 with this device on Cyclone 10 GX.
In summary: the AS x4 failure you are seeing is a hardware architectural constraint of the Cyclone 10 GX AS configuration controller — it cannot emit the Mode Byte that EBh requires on the S25FS512S. AS x1 with correct register settings is the supported path for this flash family on Cyclone 10 GX.
- Farabi_Altera
Hello,
The Cyclone 10 GX uses a fixed 10 dummy clock cycles for 1-4-4 Fast Read. However, other flash latency requirements can still be supported through the custom configuration-device settings.
For Quad I/O (1-4-4), please set the Quad I/O mode dummy clock value to:
Total dummy clocks = latency cycles + 2
For example, if the flash uses 2 mode cycles + 6 latency cycles, the total is 8 dummy clocks. If the Cyclone 10 GX instead waits for 10 clocks, the two-clock mismatch causes the flash to output the first data byte during the controller’s final two dummy-clock positions. Since Quad I/O transfers 4 bits per clock, the mismatch is 2 × 4 = 8 bits, shifting the bitstream by one byte and losing D0/D1.
The workaround is to pad those two positions with Don’t-Care data so the controller samples the real data starting at D0 with the correct alignment. The Convert Programming File utility provides separate Single I/O and Quad I/O dummy-clock settings; therefore, add +2 to the flash latency value in the Quad I/O dummy-clock field.
- Farabi_Altera
Hello, do you have further question?
SumanthHello Farabi,
Thanks for your response. I don't have any questions at the moment. I'll try your suggestions and get back to you if I need any further assistance.
- Farabi_Altera
Hello,
I will close this case first, if you have question, plesae raise new forum case. I will support you.
regards,
Farabi
- Sumanth
Hello Fabri,
Update on AS x4 configuration debuggingI performed the following tests with the Cyclone 10 GX and Infineon S25FS512S:
1. Quad I/O dummy clock = 10, Single I/O dummy clock = 8
The FPGA image did not configure successfully in AS x4 mode.
2. Quad I/O dummy clock = 8, Single I/O dummy clock = 8
The FPGA image still did not configure successfully in AS x4 mode.
3. Manual JIC data-shifting experiment
I then investigated the suggested data-alignment compensation by modifying the JIC image data. Before making the modification, I analyzed the beginning of the JIC file. The region from approximately 0x00000000 to 0x000000AA contains JIC metadata, including Quartus Prime Programmer/version information and flash/device-related information. Therefore, I preserved this region and did not apply the data shift to this metadata.
I then attempted to shift the relevant image data by two bytes based on the observed AS x4 read sequence. However, when I tried to program the modified JIC file, Quartus Programmer reported that the image was corrupted.
Saleae capture observation
While analyzing the AS x4 configuration sequence using a Saleae logic analyzer, I observed that the FPGA does not immediately start the configuration image read using EBh.
Initial access:
9Fh (Read Device ID)
↓
0Bh (Single I/O Fast Read)
Address = 0x00040000
↓
Later:
EBh (Quad I/O Read)
Address = 0x000403B8
↓
Configuration does not complete
↓
9Fh (Read Device ID) is issued again
↓
Access returns to approximately:
0x00040000
0x000403B8
↓
Sequence repeats
In my case, the EBh access occurs at an offset of:
0x000403B8 - 0x00040000 = 0x3B8
So I would like to understand the purpose of the 0x3B8 offset and the reason for the initial 0Bh read before the subsequent EBh access.
Based on the previous discussion regarding the two-clock difference between the Cyclone 10 GX AS x4 controller and the flash, I investigated whether data alignment at this location could be the cause. However, manually shifting the JIC data resulted in a corrupted JIC file.
Could you please clarify:
Is the initial 0Bh read followed by an EBh read at image base + 0x3B8 an expected Cyclone 10 GX AS x4 configuration sequence?
What is the purpose of the 0x3B8 offset?
Where exactly should the two-clock (+2) compensation be applied?
Should the compensation be handled entirely by Convert Programming File, rather than by manually modifying the JIC image?
Is there any additional requirement for the S25FS512S mode byte or dummy-cycle configuration for Cyclone 10 GX AS x4?
Thanks
Sumanth Srinivas- Farabi_Altera
Hi Sumanth, This is a detailed and well-instrumented debug report — let me address each of your questions based on what's documented for the Cyclone 10 GX AS configuration controller.
1. Is the 0Bh → EBh sequence (with EBh at base + 0x3B8) expected?
The documented AS x4 configuration sequence for Cyclone 10 GX does begin with a device ID read (9Fh / RDID), followed by a single-I/O fast read (0Bh) to read boot/header information from the flash, before switching to the quad I/O fast read (EBh) for the main configuration data stream. This is expected behavior — the controller uses the initial 0Bh read to parse the configuration header stored at the base address, which tells it where the actual bitstream begins and what mode to use. The EBh access then starts at the bitstream payload offset rather than at address 0x0.
The 0x3B8 offset you observed (0x000403B8 − 0x00040000) is consistent with this: the JIC image stores a header/metadata block at the beginning of the flash partition, and the AS controller reads through it in single-I/O mode before jumping to the bitstream start address for quad-I/O streaming. The exact size of that header region can vary with Quartus Prime version and device density, but an offset of a few hundred bytes is normal. The fact that the sequence repeats (9Fh → 0Bh → EBh → fail → 9Fh again) is the controller's retry behavior after a configuration failure — it is not looping because the address is wrong, but because the EBh read is returning data the controller cannot validate.
2. Root cause: dummy cycle mismatch for the S25FS512S (Infineon/Cypress)
AS configuration failure with Cypress/Infineon S25FSxxxS flash occurs when the flash configuration registers are not set correctly. For AS x4 (quad) configuration with the S25FSxxxS, the flash configuration registers (CR2NV/CR2V) must be set to 0xC8 before configuration starts — this encodes: AS×4 scheme, 4-byte addressing, and 8 dummy clock cycles. Why does Active Serial (AS) configuration fail with Cypress® flash S25FSxxxS in Intel® Arria® 10 devices and Intel® Cyclone® 10 GX?
Your test #2 used Quad I/O dummy = 8, which matches the 0xC8 requirement on the dummy-cycle side — but the key question is whether CR2NV/CR2V on the physical flash device was actually programmed to 0xC8 before the FPGA attempted to configure. The Cyclone 10 GX AS controller issues the EBh command with a fixed dummy-cycle count; it does not negotiate with the flash. If the flash's non-volatile register (CR2NV) still holds its factory default (which is typically not 0xC8), the flash will respond with garbage data regardless of what dummy count you set in Quartus.
Action required: Use an external processor, a JTAG-based flash programmer, or a pre-programming step to explicitly write CR2NV = 0xC8 to the S25FS512S before the FPGA configuration attempt. This is a one-time NV register write to the flash device itself, separate from the JIC programming step.
Additionally, the Programming Object File (.pof) or Raw Programming Data (.rpd) should be generated with the 'Disable EPCS/EPCQ ID check' option enabled Why does Active Serial (AS) configuration fail with Cypress® flash S25FSxxxS in Intel® Arria® 10 devices and Intel® Cyclone® 10 GX? , since the S25FS512S is not an Altera EPCQL device and its JEDEC ID will not match the expected value.
3. The two-clock compensation and JIC data shifting
Do not manually shift JIC image data. The JIC file has a structured format with CRC fields and metadata that Quartus Programmer validates — any manual byte-level edit will corrupt the file integrity check, exactly as you observed. The dummy-cycle compensation is handled at the hardware protocol level (the flash's CR2NV register setting), not by offsetting the bitstream payload in the JIC. The Convert Programming File tool generates the correct bitstream layout; the flash register must be configured to match what the AS controller expects.
4. Flash addressing requirement
Cyclone 10 GX devices only support 4-byte addressing and 10 dummy clock cycles for single I/O fast read commands (0Bh), and the AS controller is fixed to these parameters. Customizable Flash Programmer User Guide If your flash device does not support power-up 4-byte addressing mode, it cannot be used for Cyclone 10 GX configuration. Customizable Flash Programmer User Guide The S25FS512S does support 4-byte addressing, but again, CR2NV must be set to enable it in the correct mode.
Summary checklist for S25FS512S + Cyclone 10 GX AS×4:
1-Program CR2NV = 0xC8 on the flash (4-byte addressing, 8 dummy cycles for quad, AS×4 scheme) using an external host before FPGA configuration.
2-Generate your .pof/.rpd/.jic with 'Disable EPCS/EPCQ ID check' enabled in Convert Programming File.
3-Do not manually modify JIC binary data — let Quartus Prime generate the correct file.
4-Confirm the flash is in 4-byte address mode at power-up (check CR2NV, not just CR2V which is volatile).
The repeating 9Fh/0Bh/EBh sequence you captured is the retry loop — once the flash register is correctly set and the ID check is disabled, the EBh read at base+0x3B8 should return valid bitstream data and configuration should complete.
- Farabi_Altera
Hi Sumanth, do you have further question?
- Farabi_Altera
Hello Sumanth,
CR2NV / CR2V register breakdown as below:
Why Bit 6 Must Remain 01. Cyclone 10 GX Active Serial (AS x4) Uses the 1-4-4 Protocol
During AS x4 configuration, the Cyclone 10 GX configuration controller acts as the SPI master and issues the Fast Read Quad I/O (EBh) command:
- Instruction (Opcode EBh): Transmitted serially on 1 line (DATA0/SI) over 8 clock cycles.
- Address: Transmitted on 4 lines (DATA[3:0]) over 8 clock cycles (for 32-bit / 4-byte addressing).
- Mode / Latency (Dummy Cycles): Transmitted/waited on 4 lines (DATA[3:0]).
- Data Output: Read on 4 lines (DATA[3:0]).
This is strictly an Extended SPI 1-4-4 protocol. The Cyclone 10 GX hard configuration control block does not support QPI (4-4-4 protocol) during device power-up configuration.
2. What Happens if Bit 6 is Set to 1 (0xC8)
As shown in Table 26 (Configuration Register 2 Non-volatile):
- Bit 6 (QA_NV):
- 0 = Disabled: Legacy SPI protocols in use; instructions are always serial on SI (1-x-x protocols supported).
- 1 = Enabled: QPI (4-4-4) protocol in use; all instructions (including opcodes) must be driven on all 4 lines (IO[3:0]).
If bit 6 is set to 1 (0xC8):
- Upon power-up, the flash enters QPI mode and expects opcodes to arrive as 4-bit nibbles across IO[3:0] over 2 clock cycles.
- The Cyclone 10 GX drives the EBh opcode serially on DATA0 only over 8 clock cycles while DATA[3:1] remain undriven (or pulled high).
- The flash reads all 4 data lines simultaneously, receives an unrecognized opcode, and fails to decode the command.
- Consequently, no configuration bitstream is returned, CONF_DONE never transitions high, and configuration fails.
Notes: A common point of confusion is between Quad Operation Enable and QPI Protocol:
- Quad Enable (CR1V[1] / CR1NV[1] = 1): Required for AS x4. It enables the IO3/RESET# and IO2 pins for quad data transactions and permits quad read commands like EBh (1-4-4), while keeping opcode entry serial (1-line).
- QPI Enable (CR2NV[6] = 1): Forces the instruction/opcode phase itself to be 4-line (4-4-4). This is incompatible with Cyclone 10 GX AS x4.
This setting aligns with Altera AN 1013 (Using Generic QSPI Flash on Control Block-Based Devices, Section 6.1), which specifies the 4-byte register initialization write (0x01 command) for Cypress/Infineon flashes configured with Cyclone 10 GX AS x4 as: Data=0x00 0x02 0x88 0x08\text{Data} = \texttt{0x00 0x02 0x88 0x08}Data=0x00 0x02 0x88 0x08 where the 3rd byte (CR2) is explicitly configured to 0x88.
- Sumanth
Hi Farabi,
I have one quick question.I am currently setting CR2NV/CR2V to 0x88. If QPI mode is enabled by setting bit 6, the flash expects commands in the 4-4-4 protocol.
However, the Cyclone 10 GX EBh command requires the flash to operate in the 1-4-4 protocol. Therefore, I would expect QPI mode to remain disabled.
You suggested setting CR2NV/CR2V to 0xC8, which sets bit 6 as well. Could you please elaborate on why bit 6 of CR2NV/CR2V needs to be set in this configuration? Specifically, how does enabling this bit affect the EBh command sequence and its compatibility with the Cyclone 10 GX AS x4 configuration?
Regards,
Sumanth Srinivas
