Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)

Hello Fabri,  

Update on AS x4 configuration debugging

I performed the following tests with the Cyclone 10 GX and Infineon S25FS512S:

1. Quad I/O dummy clock = 10, Single I/O dummy clock = 8

   The FPGA image did not configure successfully in AS x4 mode.

2. Quad I/O dummy clock = 8, Single I/O dummy clock = 8

The FPGA image still did not configure successfully in AS x4 mode.

3. Manual JIC data-shifting experiment

I then investigated the suggested data-alignment compensation by modifying the JIC image data. Before making the modification, I analyzed the beginning of the JIC file. The region from approximately 0x00000000 to 0x000000AA contains JIC metadata, including Quartus Prime Programmer/version information and flash/device-related information. Therefore, I preserved this region and did not apply the data shift to this metadata.

I then attempted to shift the relevant image data by two bytes based on the observed AS x4 read sequence. However, when I tried to program the modified JIC file, Quartus Programmer reported that the image was corrupted.

Saleae capture observation

While analyzing the AS x4 configuration sequence using a Saleae logic analyzer, I observed that the FPGA does not immediately start the configuration image read using EBh.

Initial access:

9Fh (Read Device ID)

↓

0Bh (Single I/O Fast Read)

Address = 0x00040000

↓

Later:

EBh (Quad I/O Read)

Address = 0x000403B8

↓

Configuration does not complete

↓

9Fh (Read Device ID) is issued again

↓

Access returns to approximately:

0x00040000

0x000403B8

↓

Sequence repeats

In my case, the EBh access occurs at an offset of:

0x000403B8 - 0x00040000 = 0x3B8

So I would like to understand the purpose of the 0x3B8 offset and the reason for the initial 0Bh read before the subsequent EBh access.

Based on the previous discussion regarding the two-clock difference between the Cyclone 10 GX AS x4 controller and the flash, I investigated whether data alignment at this location could be the cause. However, manually shifting the JIC data resulted in a corrupted JIC file.

Could you please clarify:

Is the initial 0Bh read followed by an EBh read at image base + 0x3B8 an expected Cyclone 10 GX AS x4 configuration sequence?

What is the purpose of the 0x3B8 offset?

Where exactly should the two-clock (+2) compensation be applied?

Should the compensation be handled entirely by Convert Programming File, rather than by manually modifying the JIC image?

Is there any additional requirement for the S25FS512S mode byte or dummy-cycle configuration for Cyclone 10 GX AS x4?



Thanks
Sumanth Srinivas