Forum Discussion
ContributorSerdes Behavior
Hello,
We have a custom board using SDI with Cyclone 10 GX device.
For unknown reason, we found the Serdes can't locked to external signal after power on/off at about 10%.
We tried download sof once we found the serdes failed, but the status kept the same.
We check the power sequence and it met the requirement.
How can we clarify this issue.. whether it's power related or others.
5 Replies
JLee25When the issue happened, we found portion of the design is running well like Nios CPU and memory controller.
Any comments.
- anonimcs
Hi,
The first question comes to my mind is 'is the clock going to the serdes IP stable?'
- anonimcs
Hi,
No I don't mean the CLKUSR specificly. I meant the clock that you're feeding to the serdes core. If CLKUSR is the clock fed to the serdes core, then the input clock should not be the issue here. I'd check the ports of the serdes core (I have no clue about your serdes config, if you're using DPA, bitslip or FIFO reset signals etc), those should give us a better hint. But since you're observing this issue intermittently, my bet is on signal integrity (or metastability)
- JLee25
Hi,
We are using SDI and have been tried STP several XCVR locked signal.
But not able to find any clue.
One thing strange is the chip EQ locked signal to FPGA should be "High" but it's "Low" in STP.
And the locked locates in IO bank.
