Serdes Behavior

Common Altera FPGA SerDes / Transceiver Behavior Issues & Solutions

Depending on the specific SerDes issue you are trying to resolve, here are the standard solutions for the most frequent issues reported in this area:

1. Transceiver Initialization / Staggered Resets in Simulation

• Observed Behavior: Multiple independent SerDes channels (e.g., PCS-Direct on Stratix 10 or Agilex) initialize at staggered times ("strabbing") rather than simultaneously, or channel 0 fails to start immediately .
• Root Cause & Solution: This is normal hardware behavior governed by the Transceiver Reset Scheduler (TRS). In simulation, enabling the Fast reset for simu option in the Native PHY / Transceiver IP configuration bypasses the TRS sequence and forces all channels to initialize simultaneously .

2. LVDS SERDES Timing Analysis & Constraints

• Observed Behavior: Timing violations or ignored set_input_delay constraints on LVDS SERDES receiver inputs in Non-DPA mode .
• Solution: For Non-DPA mode, do not manually constrain the data lines with set_input_delay. Instead, enter the RCCS (Receiver Channel-to-Channel Skew) parameter directly in the LVDS SERDES IP core parameter editor . The Quartus Timing Analyzer then automatically generates the required SDC constraints based on the device's sampling window (SW) and transmitter channel-to-channel skew (TCCS) .

3. DPA Lock Failures in Simulation

• Observed Behavior: In simulation of RX DPA-FIFO or Soft-CDR modes, rx_dpa_locked does not assert within the expected datasheet lock window.
• Solution: The behavioral simulation models for DPA require significantly more clock edges and simulation run time than the theoretical hardware lock time (often requiring $>8\text{–}10,\mu\text{s}$ of valid toggling data). Ensure your testbench supplies adequate transitions and runs past $10,\mu\text{s}$.

4. Reference Clock Pin Restrictions (Error 18694 / Error 12499)

• Observed Behavior: Fitter errors stating that the reference clock feeding the SERDES IP / PLL is not driven by a dedicated reference clock pin from the same I/O bank.
• Solution:
  • Ensure the reference clock input is assigned to the dedicated reference clock pin belonging to the same I/O bank as the SERDES channels (for interfaces with $<23$ channels).
  • If cascading from another PLL or bank is necessary, insert a dedicated I/O PLL configured in cascade mode to feed the SERDES PLL.

5. Hardware serdes_pll_locked Behavior in PCIe HIP

• Observed Behavior: Discrepancy between documentation and hardware regarding when serdes_pll_locked asserts relative to pin_perstn.
• Solution: In real hardware, serdes_pll_locked asserts after pin_perstn is released, not before . Older user guide diagrams that depicted serdes_pll_locked permanently high prior to reset release were corrected/clarified in later revisions .

Next Step

If your issue relates to a different behavior (such as data width mapping, CDR loss-of-lock, electrical idle/LFPS, or adaptation modes), please share the device family (e.g., Agilex 5/7, Stratix 10, Cyclone V/10), IP core name, and the specific symptoms or error messages.