Forum Discussion
JLee25
Contributor
ContributorSerdes Behavior
Hello, We have a custom board using SDI with Cyclone 10 GX device. For unknown reason, we found the Serdes can't locked to external signal after power on/off at about 10%. We tried download sof ...
JLee25Contributor
ContributorHi anonimcs ,
I guess you mean the CLKUSR.
The source is a oscillator and using the same power as the flash storing FPGA bit file.
Or would you specify the which clock to serdes?
anonimcsContributor
ContributorHi,
No I don't mean the CLKUSR specificly. I meant the clock that you're feeding to the serdes core. If CLKUSR is the clock fed to the serdes core, then the input clock should not be the issue here. I'd check the ports of the serdes core (I have no clue about your serdes config, if you're using DPA, bitslip or FIFO reset signals etc), those should give us a better hint. But since you're observing this issue intermittently, my bet is on signal integrity (or metastability)
