Forum Discussion
JLee25
Contributor
ContributorSerdes Behavior
Hello, We have a custom board using SDI with Cyclone 10 GX device. For unknown reason, we found the Serdes can't locked to external signal after power on/off at about 10%. We tried download sof ...
JLee25Contributor
ContributorHi,
We are using SDI and have been tried STP several XCVR locked signal.
But not able to find any clue.
One thing strange is the chip EQ locked signal to FPGA should be "High" but it's "Low" in STP.
And the locked locates in IO bank.
