Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)

Hello, 

The Cyclone 10 GX uses a fixed 10 dummy clock cycles for 1-4-4 Fast Read. However, other flash latency requirements can still be supported through the custom configuration-device settings.

For Quad I/O (1-4-4), please set the Quad I/O mode dummy clock value to:

Total dummy clocks = latency cycles + 2

For example, if the flash uses 2 mode cycles + 6 latency cycles, the total is 8 dummy clocks. If the Cyclone 10 GX instead waits for 10 clocks, the two-clock mismatch causes the flash to output the first data byte during the controller’s final two dummy-clock positions. Since Quad I/O transfers 4 bits per clock, the mismatch is 2 × 4 = 8 bits, shifting the bitstream by one byte and losing D0/D1.

The workaround is to pad those two positions with Don’t-Care data so the controller samples the real data starting at D0 with the correct alignment. The Convert Programming File utility provides separate Single I/O and Quad I/O dummy-clock settings; therefore, add +2 to the flash latency value in the Quad I/O dummy-clock field.