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Gigiz's avatar
Gigiz
Icon for New Contributor rankNew Contributor
5 years ago

MAX10M04 / Quartus Prime Lite Edition

Good morning, I'm completing a project with MAX10M04 FPGA and Quartus Prime 20.1 Lite Edition software. The project is in the final phase, everything works fine but I have a very strange problem: I...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Gigi,


Have you simulated your design and confirmed the functionality? You should verify that your logic on RTL viewer are connecting as intended.


Regards,

Nurina


  • Gigiz's avatar
    Gigiz
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi Nurina,

    How I can do it ?

    Where can I find RTL viewer ?

    I have not experience with it, can you help me please ?

    During the compile process I have some warning, are there somethings to need fix ?

    Thanks,

    Gigi