Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the Altera documentation that the lpm_divide megafunction can be used without any clock-input. My question is: How do I get the time delay caused by the lpm_divide megafunction? In other words: How do I get the time a division 32bit/16bit will take? Do I have to use the Time Quest Analyzer? Thank you very much. Chris

If you are to design in FPGAs then you better use the clock. I have not used this function but according to lpm_divide doc there is latency of 1 clock cycle or more depending on your entry. Therefoe, If you don't use clock, I guess there will be zero latency. Don't mix up between clock latency and natural combinatorial delay. TimeQuest has nothing to do with your query. It is a tool that checks timing violations on clocked registers. If you don't use clock there will be no registers to violate = Asynchronou design. The problem is that asynchronous design is virtually abandoned in FPGAs due to logic hazards (i.e. wrong logic decisions due to uncontrolled delays. If leave your divider without clock but use synchronous design after the result then you will bump into timing problems.

how fast are you trying to run your divider? i'm not sure what kind of fmax you will hit with only 1 pipeline, maybe 10 MHz in the end you're probably going to have to add additional pipeline stages to meet fmax do you actually need a divider? do you divide by a constant, or maybe a set of a few constants? in this case you can use a multiplier instead and get away with much less pipelining and fewer resources

Like pancake said you'll need quite a few pipeline stages so that the divider can meet timing at normal clock frequencies. I've used it with 14-20 cycles in the past but that was for Stratix (one). With the pipeline stages you may increase the time for the divider to output a valid answer but it will be able to output a valid answer every clock cycle once you warm up the pipeline. So do you care about latency or throughput and do you really need a division?

--- Quote Start --- do you actually need a divider? do you divide by a constant, or maybe a set of a few constants? in this case you can use a multiplier instead and get away with much less pipelining and fewer resources --- Quote End --- Can you provide some pointers as to how one could use a multiplier when dividing by a set of constants? In my case I have a 64 bit number of which I am trying to find an exponent (base 10). Given: 2543000000, I need to arrive at 2543 & 6 (to represent 10^6). I would appreciate any help.

If you are dividing by a constant, A, you might aswell change the constant to 1/A. This way, instead of x/A, you get x * 1/A instead, usuing the multiplier, saving the large logic usage of a divider.

lpm_divider latency | Altera Community

12 Replies

Altera_Forum
Honored Contributor
14 years ago
If you are to design in FPGAs then you better use the clock.
I have not used this function but according to lpm_divide doc there is latency of 1 clock cycle or more depending on your entry. Therefoe,
If you don't use clock, I guess there will be zero latency.

Don't mix up between clock latency and natural combinatorial delay.
TimeQuest has nothing to do with your query. It is a tool that checks timing violations on clocked registers. If you don't use clock there will be no registers to violate = Asynchronou design. The problem is that asynchronous design is virtually abandoned in FPGAs due to logic hazards (i.e. wrong logic decisions due to uncontrolled delays.

If leave your divider without clock but use synchronous design after the result then you will bump into timing problems.
Altera_Forum
Honored Contributor
14 years ago
how fast are you trying to run your divider? i'm not sure what kind of fmax you will hit with only 1 pipeline, maybe 10 MHz

in the end you're probably going to have to add additional pipeline stages to meet fmax

do you actually need a divider? do you divide by a constant, or maybe a set of a few constants? in this case you can use a multiplier instead and get away with much less pipelining and fewer resources
Altera_Forum
Honored Contributor
14 years ago
Like pancake said you'll need quite a few pipeline stages so that the divider can meet timing at normal clock frequencies. I've used it with 14-20 cycles in the past but that was for Stratix (one). With the pipeline stages you may increase the time for the divider to output a valid answer but it will be able to output a valid answer every clock cycle once you warm up the pipeline. So do you care about latency or throughput and do you really need a division?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

do you actually need a divider? do you divide by a constant, or maybe a set of a few constants? in this case you can use a multiplier instead and get away with much less pipelining and fewer resources
--- Quote End ---

Can you provide some pointers as to how one could use a multiplier when dividing by a set of constants?

In my case I have a 64 bit number of which I am trying to find an exponent (base 10). Given: 2543000000, I need to arrive at 2543 & 6 (to represent 10^6). I would appreciate any help.
Altera_Forum
Honored Contributor
14 years ago
If you are dividing by a constant, A, you might aswell change the constant to 1/A. This way, instead of x/A, you get x * 1/A instead, usuing the multiplier, saving the large logic usage of a divider.
Altera_Forum
Honored Contributor
14 years ago
you'll probably want to read a bit about fixed point notation. just like in grade school, keep track of the decimal point and you'll be in good shape

first, figure out how many bits you need to get a result that's good enough for your application. here's a table that will help:

1/10 width 2^width C/10 FLOOR(D) E/C 0.1 8 256 25.6 25.0 0.0976562500 0.1 9 512 51.2 51.0 0.0996093750 0.1 10 1024 102.4 102.0 0.0996093750 0.1 11 2048 204.8 204.0 0.0996093750 0.1 12 4096 409.6 409.0 0.0998535156 0.1 13 8192 819.2 819.0 0.0999755859 0.1 14 16384 1638.4 1638.0 0.0999755859 0.1 15 32768 3276.8 3276.0 0.0999755859 0.1 16 65536 6553.6 6553.0 0.0999908447

figure out how many integer bits you need. if you don't mind wasting a couple bits, and are using 2's compliment, you might leave the MSb as sign/integer and have the following bits be fraction bits. then in your product, note the location of the decimal point

this seems like somewhat of a common problem. this is basically a base10 barrel shifter, right?
Altera_Forum
Honored Contributor
14 years ago
Thanks, 'Tricky' and 'thepancake' for your replies. :)

I see your point. But what would you use to do the multiplication? The standard Verilog '*' operator? Or a Floating Point Multiply function from the Megafunction library?

If using a multiply megafunction, I will need to try & see if the output latency or area be any better than the lpm_divide latency.
Altera_Forum
Honored Contributor
14 years ago
the fixed point * operator or an lpm_mult

what about using the Altera floating point megafunction to convert your fixed number into an IEEE-ish float. they do the heavy lifting of finding the mantissa and exponent for you
Altera_Forum
Honored Contributor
14 years ago
Turns out that is the best option. Many thanks!
Altera_Forum
Honored Contributor
14 years ago
According to your post# 5, you seem to work on a pure integer arithmetic problem. It sounds strange, that it can be better solved by floating point means. Even the standard IEEE double format won't be sufficient to guarantee avoidance of rounding errors.

Forum Discussion

lpm_divider latency

12 Replies

Recent Discussions

QSPI DDR Interface with Cyclone10LP: Maximum frequency

System PLL of Agliex5 PCIE example design cannot be locked after configuration

MAX 10 FPGA POR trip Levsl and tRAMP

MAX10 fiftyfivenm encrypted module

PCIe not working (no enumeration) Agilex™ 5 FPGA E-Series 065B Modular Development Kit