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Altera_Forum
Honored Contributor
14 years agolpm_divider latency
Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
Altera_Forum
Honored Contributor
14 years agoLike pancake said you'll need quite a few pipeline stages so that the divider can meet timing at normal clock frequencies. I've used it with 14-20 cycles in the past but that was for Stratix (one). With the pipeline stages you may increase the time for the divider to output a valid answer but it will be able to output a valid answer every clock cycle once you warm up the pipeline. So do you care about latency or throughput and do you really need a division?