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Altera_Forum
Honored Contributor
Honored Contributorlpm_divider latency
Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
Altera_ForumHonored Contributor
Honored ContributorThanks, 'Tricky' and 'thepancake' for your replies. :)
I see your point. But what would you use to do the multiplication? The standard Verilog '*' operator? Or a Floating Point Multiply function from the Megafunction library? If using a multiply megafunction, I will need to try & see if the output latency or area be any better than the lpm_divide latency.
