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Altera_Forum
Honored Contributor
Honored Contributorlpm_divider latency
Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
Altera_ForumHonored Contributor
Honored Contributorthe fixed point * operator or an lpm_mult
what about using the Altera floating point megafunction to convert your fixed number into an IEEE-ish float. they do the heavy lifting of finding the mantissa and exponent for you
