lpm_divider latency

If you are to design in FPGAs then you better use the clock.

I have not used this function but according to lpm_divide doc there is latency of 1 clock cycle or more depending on your entry. Therefoe,

If you don't use clock, I guess there will be zero latency.

Don't mix up between clock latency and natural combinatorial delay.

TimeQuest has nothing to do with your query. It is a tool that checks timing violations on clocked registers. If you don't use clock there will be no registers to violate = Asynchronou design. The problem is that asynchronous design is virtually abandoned in FPGAs due to logic hazards (i.e. wrong logic decisions due to uncontrolled delays.

If leave your divider without clock but use synchronous design after the result then you will bump into timing problems.