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Altera_Forum
Honored Contributor
14 years agolpm_divider latency
Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
Altera_Forum
Honored Contributor
14 years agoyou'll probably want to read a bit about fixed point notation. just like in grade school, keep track of the decimal point and you'll be in good shape
first, figure out how many bits you need to get a result that's good enough for your application. here's a table that will help:
1/10 width 2^width C/10 FLOOR(D) E/C
0.1 8 256 25.6 25.0 0.0976562500
0.1 9 512 51.2 51.0 0.0996093750
0.1 10 1024 102.4 102.0 0.0996093750
0.1 11 2048 204.8 204.0 0.0996093750
0.1 12 4096 409.6 409.0 0.0998535156
0.1 13 8192 819.2 819.0 0.0999755859
0.1 14 16384 1638.4 1638.0 0.0999755859
0.1 15 32768 3276.8 3276.0 0.0999755859
0.1 16 65536 6553.6 6553.0 0.0999908447
figure out how many integer bits you need. if you don't mind wasting a couple bits, and are using 2's compliment, you might leave the MSb as sign/integer and have the following bits be fraction bits. then in your product, note the location of the decimal point this seems like somewhat of a common problem. this is basically a base10 barrel shifter, right?