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Altera_Forum
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14 years ago

lpm_divider latency

Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

According to your post# 5, you seem to work on a pure integer arithmetic problem. It sounds strange, that it can be better solved by floating point means. Even the standard IEEE double format won't be sufficient to guarantee avoidance of rounding errors.