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Honored Contributor
Honored Contributorlpm_divider latency
Hi, I am new in VHDL and Altera FPGA. I am currently working with a Cyclone III. I want to use the megafunction lpm_divide to do a signed 32 bit / signed 16 bit division. I read in the A...
Altera_ForumHonored Contributor
Honored Contributorhow fast are you trying to run your divider? i'm not sure what kind of fmax you will hit with only 1 pipeline, maybe 10 MHz
in the end you're probably going to have to add additional pipeline stages to meet fmax do you actually need a divider? do you divide by a constant, or maybe a set of a few constants? in this case you can use a multiplier instead and get away with much less pipelining and fewer resources
