Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hello,

Just checking with your observation on the extra cycle wider , do you observe any failure symptom? If yes, can you explain what is the failure?

regards,

Farabi

Hello,

May I know if you have any updates on clarification needed?

Hello,

When W_OOB is asserted to high, the FIFO master reads from the FIFO and discards data as long as RXF_N is asserted. RXF_N may assert multiple times while W_OOB is asserted. In streaming mode, the master read and master write data count sequence is reset depending on the corresponding OOB signal assertion.

From the diagram, the RXF_N is not controlled by Cyclone V FPGA. RXF_N may get asserted multiple times while W_OOB is asserted. So you control the W_OOB signal.

regards,

Farabi

Diagram from FTDI user guide:

Hi,

looking at FT601 bus timing requirements in datasheet, I believe the problem could be caused by setting FPGA generated signals (in this case OE_N, RD_N) on the wrong clock edge. The problem doesn't appear with slow Cyclone V which produces sufficient output delay to still fulfill FT601 input signal hold requirement of 4.8 ns. Faster Stratix 10 apparently doesn't. Output delay constraints seem not to work as intended.

100 MHz clocked Signaltap isn't able to visualize the problem. A sufficient fast oscilloscope or LA can.

Regards
Frank

Hi Frank,

Thanks for looking into this. I will reconfirm the clock edge. I did notice about the delay constraints not working as intended in Stratix. The chip is capable of 100MHz but I am using it at 66 MHz.

Best,

Bharat

Hi Bharat,

Do you have any updates on the clock edge? Have you check it as suggested?

Regards,

Aqid

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Hi,

As suggested above the issue seems to be stemming from the fast IOs of Stratix while cyclone is providing enough delay for hold time, I think. The design is working on positive edge which might causing the suggested hold time violations. I still fail to understand how this would affect just the RXF_N signal widening it but there are no data bus errors. I would have imagined if there were such hold time issues, then the 32bit wide data bus would have been more susceptible to bit errors.

In any case, the other suggestion using the oscilloscope to view the signals is not possible as the board is in a remote location with no access to oscilloscope. Somebody had suggested to use a higher frequency clock to sample the complete FTDI interface along with the FTDI clock and it might give some idea about whats happening. I will give it a try and share what I see. .

Also, will give try to convert the design to negative edge at the FTDI IO Signals,.

Best,

Bharat

Hi Bharat,

Any updates on the issue?