Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hello,

When W_OOB is asserted to high, the FIFO master reads from the FIFO and discards data as long as RXF_N is asserted. RXF_N may assert multiple times while W_OOB is asserted. In streaming mode, the master read and master write data count sequence is reset depending on the corresponding OOB signal assertion.

From the diagram, the RXF_N is not controlled by Cyclone V FPGA. RXF_N may get asserted multiple times while W_OOB is asserted. So you control the W_OOB signal.

regards,

Farabi