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BKB
Occasional Contributor
Occasional ContributorInput signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
Farabi_Altera
Regular Contributor
Regular ContributorHello,
When W_OOB is asserted to high, the FIFO master reads from the FIFO and discards data as long as RXF_N is asserted. RXF_N may assert multiple times while W_OOB is asserted. In streaming mode, the master read and master write data count sequence is reset depending on the corresponding OOB signal assertion.
From the diagram, the RXF_N is not controlled by Cyclone V FPGA. RXF_N may get asserted multiple times while W_OOB is asserted. So you control the W_OOB signal.
regards,
Farabi
