Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi,

looking at FT601 bus timing requirements in datasheet, I believe the problem could be caused by setting FPGA generated signals (in this case OE_N, RD_N) on the wrong clock edge. The problem doesn't appear with slow Cyclone V which produces sufficient output delay to still fulfill FT601 input signal hold requirement of 4.8 ns. Faster Stratix 10 apparently doesn't. Output delay constraints seem not to work as intended.

100 MHz clocked Signaltap isn't able to visualize the problem. A sufficient fast oscilloscope or LA can.

Regards
Frank