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BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
Board Debug
Generic Io
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.