Forum Discussion

BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
Board Debug
Generic Io
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


Just checking with your observation on the extra cycle wider , do you observe any failure symptom? If yes, can you explain what is the failure?


regards,

Farabi