Forum Discussion
BKB
Occasional Contributor
Occasional ContributorInput signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
May I know if you have any updates on clarification needed?
BKBOccasional Contributor
Occasional ContributorHi,
The issue still persists. There is no failure symptom or mechanism other than RXF_n signal from FTDI chip through the board is widened by a cycle.
Best,
Bharat
