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BKB's avatar
BKB
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9 months ago

Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
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Generic Io
BKB's avatar
BKB
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

Hi Frank,

Thanks for looking into this. I will reconfirm the clock edge. I did notice about the delay constraints not working as intended in Stratix. The chip is capable of 100MHz but I am using it at 66 MHz.

Best,

Bharat