Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi,

As suggested above the issue seems to be stemming from the fast IOs of Stratix while cyclone is providing enough delay for hold time, I think. The design is working on positive edge which might causing the suggested hold time violations. I still fail to understand how this would affect just the RXF_N signal widening it but there are no data bus errors. I would have imagined if there were such hold time issues, then the 32bit wide data bus would have been more susceptible to bit errors.

In any case, the other suggestion using the oscilloscope to view the signals is not possible as the board is in a remote location with no access to oscilloscope. Somebody had suggested to use a higher frequency clock to sample the complete FTDI interface along with the FTDI clock and it might give some idea about whats happening. I will give it a try and share what I see. .

Also, will give try to convert the design to negative edge at the FTDI IO Signals,.

Best,

Bharat