Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have User IO based asynchrnonous reset. In this case a DFF with enable would have the following code: always @(posedge clk) if(enable) q <= data; What will the value of this register be before the DFF is enabled? Is this value guaranteed? Does this act the same way across all Altera device families? What about other PLD vendors?

See page 6-36 of the HDL coding guidelines: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Registers should power up with a '0' value. You can also specify a power-up value using an assignment. There is the NOT-gate pushback optimization that can change the behavior in some cases but I suspect you don't need to worry about that. Jake

in verilog you have the initial block after the modul declaration module mymodul ( myclk , myreg); input myclk; output myreg; initial begin myreg <= myinitvalue; end reg myreg; always @ ( posedge myclk ) myreg <= myreg + 1; endmodule but have a look at the quartus settings about initial values, i am currently unshure which one but i think the is one settings about that. regards michael

Thanks! The documentation you linked is very useful.

--- Quote Start --- always @(posedge clk) if(enable) q <= data; What will the value of this register be before the DFF is enabled? Is this value guaranteed? Does this act the same way across all Altera device families? What about other PLD vendors? --- Quote End --- You must be careful about this. We recently have a thread about the reliability of power-up values. Unless the "Power-up Don't Care" logic option is enabled, then the power-up value is fixed. In this case, without any async signals and specific power-up value, it would be zero. However, all registers have a chip-wide async reset that is always enabled and it is released just before entering user mode. This is how the power-up value is actually set. The problem is that this chip-wide async reset is not released synchronously to any clock whatsoever. Another problem with implicit power-up values is that simulators are usually not aware about them.

It is not wise to depend on powerup feature for every single register. What I normally do is have an internal reset when fpga is configured. Though this will need a logic that starts low but at least it uses few registers e.g. counter going up from 0 to 15 and stops there, release reset at count 15.

Initial DFF values after FPGA programming

22 Replies

Altera_Forum
Honored Contributor
16 years ago
See page 6-36 of the HDL coding guidelines:
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Registers should power up with a '0' value. You can also specify a power-up value using an assignment. There is the NOT-gate pushback optimization that can change the behavior in some cases but I suspect you don't need to worry about that.

Jake
Altera_Forum
Honored Contributor
16 years ago
in verilog you have the initial block after the modul declaration

module mymodul ( myclk , myreg);

input myclk;
output myreg;

initial
begin
myreg <= myinitvalue;
end

reg myreg;
always @ ( posedge myclk )
myreg <= myreg + 1;

endmodule

but have a look at the quartus settings about initial values, i am currently unshure which one but i think the is one settings about that.

regards

michael
Altera_Forum
Honored Contributor
16 years ago
Thanks! The documentation you linked is very useful.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
always @(posedge clk) if(enable) q <= data;

What will the value of this register be before the DFF is enabled? Is this value guaranteed? Does this act the same way across all Altera device families? What about other PLD vendors?
--- Quote End ---

You must be careful about this. We recently have a thread about the reliability of power-up values.

Unless the "Power-up Don't Care" logic option is enabled, then the power-up value is fixed. In this case, without any async signals and specific power-up value, it would be zero.

However, all registers have a chip-wide async reset that is always enabled and it is released just before entering user mode. This is how the power-up value is actually set. The problem is that this chip-wide async reset is not released synchronously to any clock whatsoever.

Another problem with implicit power-up values is that simulators are usually not aware about them.
Altera_Forum
Honored Contributor
16 years ago
It is not wise to depend on powerup feature for every single register. What I normally do is have an internal reset when fpga is configured. Though this will need a logic that starts low but at least it uses few registers e.g. counter going up from 0 to 15 and stops there, release reset at count 15.
Altera_Forum
Honored Contributor
16 years ago
I agree with kaz. All of my designs have a reset controller that provides a timed synchronous reset on FPGA power up.

Jake
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
It is not wise to depend on powerup feature for every single register. What I normally do is have an internal reset when fpga is configured. Though this will need a logic that starts low but at least it uses few registers e.g. counter going up from 0 to 15 and stops there, release reset at count 15.
--- Quote End ---

Since we can't depend on the power-up state of any of the registers, is there any protection if the registers used in this reset counter fail to initialize properly? For instance, if they happened to initialize to all 1s the reset would be released immediately (or perhaps never be asserted at all). There are probably ways around this. Perhaps reading the initial value of the counter into a second register, then incrementing the counter until the counter rolls over and the two registers are equal again to release the internal reset?

This might be overkill :)
Altera_Forum
Honored Contributor
16 years ago
I usually use a power-up value assignment on the reset counter to ensure it powers up appropriately. But then that's the only register you have to worry about if everything else is reset. That's really the best way.

Jake
Altera_Forum
Honored Contributor
16 years ago
It is a good idea as detection mechanism but is certainly overkill. I have used this method and tested my circuit several thousands of time using software setup overnight and weekend. I believe having few registers starting at zero
is not a problem stastiscally.
Altera_Forum
Honored Contributor
16 years ago
--- Quote Start ---
Since we can't depend on the power-up state of any of the registers
--- Quote End ---
Power-up state can be considered reliable, the problem is with asynchronous release of power-up reset. As a consequence, a counter or state-machine can advance to an unexpected next state on a clock edge that coincides with reset release in some cases. But it can't advance to any arbitrary state, because each single register bit either keeps the reset state or takes the next state.

E.g. a one state hot state variable, advancing regularly from 1000 to 0100 can wrongly take 0000 or 1100, but no other state. A counter counting from reset state 0000 to next state 0001 in contrast can keep the reset state at worse. This is the reason, why the said reset controller counter always works reliably in my opinion. So if you want to provide an synchronous released reset but don't have an external reset signal, it's a good way.

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Initial DFF values after FPGA programming

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