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Altera_Forum's avatar
Altera_Forum
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16 years ago

Initial DFF values after FPGA programming

Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I usually use a power-up value assignment on the reset counter to ensure it powers up appropriately. But then that's the only register you have to worry about if everything else is reset. That's really the best way.

Jake