Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It is not wise to depend on powerup feature for every single register. What I normally do is have an internal reset when fpga is configured. Though this will need a logic that starts low but at least it uses few registers e.g. counter going up from 0 to 15 and stops there, release reset at count 15. --- Quote End --- Since we can't depend on the power-up state of any of the registers, is there any protection if the registers used in this reset counter fail to initialize properly? For instance, if they happened to initialize to all 1s the reset would be released immediately (or perhaps never be asserted at all). There are probably ways around this. Perhaps reading the initial value of the counter into a second register, then incrementing the counter until the counter rolls over and the two registers are equal again to release the internal reset? This might be overkill :)
