Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Initial DFF values after FPGA programming

Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

in verilog you have the initial block after the modul declaration

module mymodul ( myclk , myreg);

input myclk;

output myreg;

initial

begin

myreg <= myinitvalue;

end

reg myreg;

always @ ( posedge myclk )

myreg <= myreg + 1;

endmodule

but have a look at the quartus settings about initial values, i am currently unshure which one but i think the is one settings about that.

regards

michael