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Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored ContributorSee page 6-36 of the HDL coding guidelines:
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Registers should power up with a '0' value. You can also specify a power-up value using an assignment. There is the NOT-gate pushback optimization that can change the behavior in some cases but I suspect you don't need to worry about that. Jake
