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Altera_Forum's avatar
Altera_Forum
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17 years ago

Initial DFF values after FPGA programming

Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It is a good idea as detection mechanism but is certainly overkill. I have used this method and tested my circuit several thousands of time using software setup overnight and weekend. I believe having few registers starting at zero

is not a problem stastiscally.