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always @(posedge clk)
if(enable) q <= data;
What will the value of this register be before the DFF is enabled? Is this value guaranteed? Does this act the same way across all Altera device families? What about other PLD vendors?
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You must be careful about this. We recently have a thread about the reliability of power-up values.
Unless the "Power-up Don't Care" logic option is enabled, then the power-up value is fixed. In this case, without any async signals and specific power-up value, it would be zero.
However, all registers have a chip-wide async reset that is always enabled and it is released just before entering user mode. This is how the power-up value is actually set. The problem is that this chip-wide async reset is not released synchronously to any clock whatsoever.
Another problem with implicit power-up values is that simulators are usually not aware about them.
Honored Contributor
