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Since we can't depend on the power-up state of any of the registers
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Power-up state can be considered reliable, the problem is with asynchronous release of power-up reset. As a consequence, a counter or state-machine can advance to an unexpected next state on a clock edge that coincides with reset release in some cases. But it can't advance to any arbitrary state, because each single register bit either keeps the reset state or takes the next state.
E.g. a one state hot state variable, advancing regularly from 1000 to 0100 can wrongly take 0000 or 1100, but no other state. A counter counting from reset state 0000 to next state 0001 in contrast can keep the reset state at worse. This is the reason, why the said reset controller counter always works reliably in my opinion. So if you want to provide an synchronous released reset but don't have an external reset signal, it's a good way.
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