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Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored ContributorIt is not wise to depend on powerup feature for every single register. What I normally do is have an internal reset when fpga is configured. Though this will need a logic that starts low but at least it uses few registers e.g. counter going up from 0 to 15 and stops there, release reset at count 15.
