Initial DFF values after FPGA programming

I agree, that asynchronous release of reset involves the possibility of timing violations and thus, metastability must be considered, in principle.

My main intention was to clarify, that power-up values are not generally unreliable. There are however particular effects of the asynchronous released reset that should be analysed in detail.

It's no problem to extend my above counter example by analysis of possible metastability. You have a state transition 0000 -> 0001. If we assume a metastable state for bit 0, we get possible next states of 0000, 0001 or 0010, but no other possible coding, because bit 1 to 3 are stable at 0.

Thus, in my opinion, the discussed reset counter is metastable proof.

As another point, you shouldn't forget about the likelihood of metastability. I doubt, that you have real chances to reproduce it in an occasional triggered reset circuit. I'm under the impression, that many designers, who talk about metastability observations actually experienced simple timing violations by asynchronous signals.

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I will strongly believe that powerup reset release will not be made any close to any clk edge. The silicon people wouldn't let that happen on the very first clk edge or can they?

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I don't think the silicon people have any way to prevent that.

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Since the asynchronous signal is a reset/preset, we are not violating the flip-flop's Data input to rising-clock setup time, but instead de-asserting a preset while the clock is rising...

I do not know if this can lead to metastability the same way setup time violations can.

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I do think that reset release has a minimum setup requirement, and if that is violated then it can produce metastability.

I am a bit confused now...because any release near clk edge will violate Tsu/Th

I will strongly believe that powerup reset release will not be made any close to any clk edge. The silicon people wouldn't let that happen on the very first clk edge or can they?

After all we are told to take care of reset release at field.

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I do not know if this can lead to metastability the same way setup time violations can.

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i have seen it affect a design in this way. i was convinced it was a timing issue because fit to fit and even device to device behavior would vary. in the end it was solved by synchronizing the reset in a second clock domain.

:eek:

Here. You can use this. Use the assignment editor in Quartus to specify a power-up level of 0 to "count" within your design instance.

Jake

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I was going to say the same.

But I wonder just out of curiosity, and would like yours and other experts opinion, if this is really 100% foolproof. Isn't it possible that the async reset release could produce setup/hold violations on the register output? If this is possible, then the next register in the counter could, in theory, become metastable.

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If this is the case, are the bits in your counter/shift register acting as synchronization registers? Since the asynchronous signal is a reset/preset, we are not violating the flip-flop's Data input to rising-clock setup time, but instead de-asserting a preset while the clock is rising. I assume from what FmV said that the problem is some registers interpret this as a reset followed by a rising clock, and other interpreting it as a rising clock followed by a reset.

I do not know if this can lead to metastability the same way setup time violations can.

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I'll try to find the thread about the reliability of power-up values that vjAlter mentioned and read up on it more.

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http://www.alteraforum.com/forum/showthread.php?t=6067

Not really much more elaboration in that thread than here. Except perhaps that it was stressed, the probably obvious, that the reset logic must be done separately on each clock domain.