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Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I'll try to find the thread about the reliability of power-up values that vjAlter mentioned and read up on it more. --- Quote End --- http://www.alteraforum.com/forum/showthread.php?t=6067 Not really much more elaboration in that thread than here. Except perhaps that it was stressed, the probably obvious, that the reset logic must be done separately on each clock domain.
