Initial DFF values after FPGA programming

I agree, that asynchronous release of reset involves the possibility of timing violations and thus, metastability must be considered, in principle.

My main intention was to clarify, that power-up values are not generally unreliable. There are however particular effects of the asynchronous released reset that should be analysed in detail.

It's no problem to extend my above counter example by analysis of possible metastability. You have a state transition 0000 -> 0001. If we assume a metastable state for bit 0, we get possible next states of 0000, 0001 or 0010, but no other possible coding, because bit 1 to 3 are stable at 0.

Thus, in my opinion, the discussed reset counter is metastable proof.

As another point, you shouldn't forget about the likelihood of metastability. I doubt, that you have real chances to reproduce it in an occasional triggered reset circuit. I'm under the impression, that many designers, who talk about metastability observations actually experienced simple timing violations by asynchronous signals.