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I was going to say the same.
But I wonder just out of curiosity, and would like yours and other experts opinion, if this is really 100% foolproof. Isn't it possible that the async reset release could produce setup/hold violations on the register output? If this is possible, then the next register in the counter could, in theory, become metastable.
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If this is the case, are the bits in your counter/shift register acting as synchronization registers? Since the asynchronous signal is a reset/preset, we are not violating the flip-flop's Data input to rising-clock setup time, but instead de-asserting a preset while the clock is rising. I assume from what FmV said that the problem is some registers interpret this as a reset followed by a rising clock, and other interpreting it as a rising clock followed by a reset.
I do not know if this can lead to metastability the same way setup time violations can.
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