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Altera_Forum's avatar
Altera_Forum
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17 years ago

Initial DFF values after FPGA programming

Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

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I will strongly believe that powerup reset release will not be made any close to any clk edge. The silicon people wouldn't let that happen on the very first clk edge or can they?

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I don't think the silicon people have any way to prevent that.