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Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Since the asynchronous signal is a reset/preset, we are not violating the flip-flop's Data input to rising-clock setup time, but instead de-asserting a preset while the clock is rising... I do not know if this can lead to metastability the same way setup time violations can. --- Quote End --- I do think that reset release has a minimum setup requirement, and if that is violated then it can produce metastability.
