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Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I do not know if this can lead to metastability the same way setup time violations can. --- Quote End --- i have seen it affect a design in this way. i was convinced it was a timing issue because fit to fit and even device to device behavior would vary. in the end it was solved by synchronizing the reset in a second clock domain. :eek:
