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Altera_Forum
Honored Contributor
Honored ContributorInitial DFF values after FPGA programming
Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_ForumHonored Contributor
Honored ContributorLook folks, there is no perfect circuit. We do the best we can and try to make our circuit immune to 99.9% of the wild corner cases. Create a synchronous reset circuit and specify the power-up value.
