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Altera_Forum's avatar
Altera_Forum
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10 years ago

Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block?

I would like to use Independent Multiplier Mode of DSP block.

While the similar module dsp1a+dsp1b (top level is now dsp1b) uses one DSP block, as expected.

module dsp1a(input wire [7:0] a1, input wire [7:0] b1,

input wire [7:0] a2, input wire [7:0] b2,

output wire [15:0] y1,

output wire [15:0] y2

);//infers 2 DSP when top-level: BAD

assign y1 = a1 * b1;

assign y2 = a2 * b2;

endmodule

module dsp1b(input wire [7:0] a1, input wire [7:0] b1,

input wire [7:0] a2, input wire [7:0] b2,

output wire [15:0] y

);//infers 1 DSP when top-level: OK

wire [15:0] y1;

wire [15:0] y2;

dsp1a dsp1 (.a1(a1), .b1(b1), .a2(a2), .b2(b2), .y1(y1), .y2(y2));

assign y = y1 + y2;

endmodule

Thanks in advance

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you for reply. But I tried inferring 26 multipliers on device having 25 DSP blocks and it not fit. So automatic merging multipliers to DSP seems doesn't occur. I tried also different speed/balance optimization.

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    do you mean that you are using 26 independent 8x8 multiples? did you see fitting error or any other errors? How many DSP blocks are occupied?

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Rather than filling an FPGA until all of its DSP resources are used, you can use logiclock to force the design into a smaller area.

    If for example, you expect to fit two multipliers into a single DSP block, and you have used the appropriate DSP block inference HDL code, then it will work. If it does not, then I would first recommend instantiating an IP Catalog instance and confirm that you can get the DSP logic packed into a single block. Then go and use the templates provided in the Quartus II editor (assuming there is some DSP logic close to what you want). Basically you'll need to "debug" why your inference code is not working. It could be something simple like the use of a reset control in your HDL that does not exist in the underlying resource. I'd recommend dumbing-down your design until it packs correctly, and then edit and synthesize to determine what additional logic causes it to fail.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you. I tried: verilog and VHDL modules with configurations that matched DSP block schematic (seen both in Chip Planner and in datasheet [1]), recommended coding styles, templates, multiplier drawn in BDF schematic, altera lpm_mult IP functions. In every case the result was 2 DSP blocks. But in [1], table 3-4 on page 49 it is shown that DSP block supports three 9x9 multiplications in independent configuration. Now I am trying to explicitly pack DSP input registers (three 9bit -> 27bit input), without success.

    [1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    --- Quote Start ---

    Thank you. I tried: verilog and VHDL modules with configurations that matched DSP block schematic (seen both in Chip Planner and in datasheet [1]), recommended coding styles, templates, multiplier drawn in BDF schematic, altera lpm_mult IP functions. In every case the result was 2 DSP blocks.

    --- Quote End ---

    Sounds like you have tried everything :)

    --- Quote Start ---

    But in [1], table 3-4 on page 49 it is shown that DSP block supports three 9x9 multiplications in independent configuration. Now I am trying to explicitly pack DSP input registers (three 9bit -> 27bit input), without success.

    [1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

    --- Quote End ---

    File a Service Request with Altera directly. They were the ones who suggested I try LogicLock when I had a similar question. Hopefully they can help you with this question.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi all,

    I am facing the same issue of jenii. Both Quartus v14 and v15 does not pack three multipliers 9x9bit within the same DSP block. I tried also with the lpm_mult and altmult instances with no luck.

    Jenii, have you got any news from Altera?

    Cheers,

    Luca
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Hi Luca,

    still I have not good news. If I find the solution, I will write it here.

    Cheers, Jan

    --- Quote Start ---

    Hi all,

    I am facing the same issue of jenii. Both Quartus v14 and v15 does not pack three multipliers 9x9bit within the same DSP block. I tried also with the lpm_mult and altmult instances with no luck.

    Jenii, have you got any news from Altera?

    Cheers,

    Luca

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    pls try to create a simple design which consist only three multipliers 9x9 and then logic lock this design with a region that consist only one DSP block. It should work.