Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

Thank you. I tried: verilog and VHDL modules with configurations that matched DSP block schematic (seen both in Chip Planner and in datasheet [1]), recommended coding styles, templates, multiplier drawn in BDF schematic, altera lpm_mult IP functions. In every case the result was 2 DSP blocks. But in [1], table 3-4 on page 49 it is shown that DSP block supports three 9x9 multiplications in independent configuration. Now I am trying to explicitly pack DSP input registers (three 9bit -> 27bit input), without success.